Computer buses are generally employed to transfer data between two or more elements in a computer system, such as between a microprocessor and random access memory, or from a floppy disk drive to a cache. Efficiently designed bus architecture is of increasing concern as the processing speeds of the elements coupled by the buses continue to increase.
One form of bus architecture comprises a ring topology. Generally, in a ring topology, information, which can comprise both commands to processing elements (PE) and data employed by the PE, is passed from PE to PE in a circular, pipe-lined manner. Furthermore, a plurality of ring topologies can be coupled together and share information. In other words, data transfers can occur from a local bus ring to a remote bus ring.
Bus rings also typically have a plurality of caches that store and transmit information that is to be forwarded through the bus ring topology. Each cache of the bus ring can have an associated processor unit (PU) and an associated cache investigator. Generally, the cache investigator responds to data transfer requests that it receives from the local bus ring, although the requests can originate on a remote bus ring. Generally, the cache investigator determines if its associated cache has the requested data, and the status of that data. Status can be generally defined as whether the data is “exclusive” (only that cache has a copy of the data from system memory), “shared” (that cache and probably one or more other caches have a copy of the data from system memory) or “modified” (the data has been altered since it was loaded from system memory). As part of the reply, the status is then broadcast to the local bus ring and from there to any coupled remote bus rings.
This status information is evaluated by data transfer logic to determine the appropriate action to take regarding the data transfer request. If data in a cache has been modified, this modified data is transferred to the requesting PE, whether on not the cache containing the modified data is on a local bus ring or a remote bus ring.
In conventional systems, if the data in the cache is unmodified, the data transfer logic typically instructs the bus ring to perform a cache-to-cache transfer of unmodified data if both the source cache and the destination cache are on the same bus ring (“node”), as this is generally regarded as faster than the transfer from shared memory to a local node. If the unmodified cache data is on a remote node, the transfer logic typically instructs the bus ring to download the information from the shared memory instead of from the remote cache, as this is generally regarded as faster than the data transfer from a remote node to a local node.
However, there are problems associated with this design approach. The time and resources required for data transfers to and from the local cache can be a substantial impediment to efficient utilization of the bus rings. Therefore, a bus data transfer system is needed which solves at least some of the problems of conventional bus data transfer systems.